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Unfortunately, Dedicated-IO requires a nonuniform design for each layer , and its DRAM energy consumption scales linearly with the number of layers. Our second approach, Cascaded-IO, solves both issues by instead time multiplexing all of the TSVs across layers. Cascaded-IO reduces DRAM energy consumption by lowering the operating frequency of higher layers. Our evaluations show that SMLA provides significant performance improvement and energy reduction across a variety of workloads (55%/18% on average for multiprogrammed workloads, respectively) over a baseline 3D-stacked DRAM, with low overhead.

The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.

Other banks reported a CIR of more than 40%, while MBBank achieved a CIR of just 16.7% in 2020. As Figure 6a shows, in the case of a two layer 3D-stacked DRAM, each layer has its own IO connection, whose width is half of the total IO width W . 6 For our two-layer example in Figure 6a, we can increase the IO frequency, and therefore the bandwidth, to twice that of the baseline 3D-stacked DRAM by having each layer send two sets of 64-bit data at 2F frequency. Figure 7 compares the detailed organizations of existing 3D-stacked DRAM , where all layers share all TSVs, and a 3D-stacked DRAM using Dedicated-IO . TSVs provide two major benefits to increase memory bandwidth and energy efficiency. First, due to the small feature size of modern TSV technologies (10 − 35µm pitch for TSVs vs. 90µm pitch for conventional pads), 3D-stacked DRAM can integrate hundreds of TSVs for its connections between layers.

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